library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Use ieee.std_logic_textio.all; -- Synopsys社のstd_logic_textioパッケージ
use STD.textio.all;
-- VHDL標準のtextioだけでなくSynopsys社のstd_logic_textioパッケージも使用する．
-- 信号タイプがbitやbit_vectorであればstd_logic_textioパッケージを用いる必要はないが
-- std_logicやstd_logic_vectorでは必要．

-- for to_hstring
--library ieee_proposed;
--use ieee_proposed.std_logic_1164_additions.all;

use work.txt_util.all;

library modelsim_lib;
use modelsim_lib.util.all;

entity vrc7_tb is end;

architecture SIM of vrc7_tb is

component vrc7_fifo
port(
	p_reset : in std_logic;
	m_clock : in std_logic;
	run     : in std_logic;
	ready   : in std_logic;
	A       : in std_logic;
	D       : in std_logic_vector(7 downto 0);
	write   : in std_logic;
	sound   : out std_logic_vector(12 downto 0)
);
end component;

	constant CYCLE : time := 20 ns;

	signal rst_n, clk : std_logic;

	signal run : std_logic;
	signal count : std_logic_vector(3 downto 0);

	signal cpu_run : std_logic;
	signal cpu_count : std_logic_vector(4 downto 0);

	signal we, sel : std_logic;
	signal data : std_logic_vector(7 downto 0);
	signal sound : std_logic_vector(12 downto 0);
	signal sound_en : std_logic;

	signal stage : integer range 0 to 3;
	signal slot : integer range 0 to 17;

procedure write(
	wadrs : in std_logic_vector(7 downto 0);
	wdata : in std_logic_vector(7 downto 0);
	signal we : out std_logic;
	signal sel : out std_logic;
	signal data : out std_logic_vector(7 downto 0)
) is
begin

-- LDA(2)+STA(4)=6cpu_run

		for I in 0 to 5 loop
			wait until cpu_run='1';
		end loop;
		we <= '1';
		sel <= '0';
		data <= wadrs;
		wait until clk'event and clk='1';
		we <= '0';

		for I in 0 to 5 loop
			wait until cpu_run='1';
		end loop;
		we <= '1';
		sel <= '1';
		data <= wdata;
		wait until clk'event and clk='1';
		we <= '0';

-- 書き込みwaitはvrc7_fifoに実装
--		for I in 0 to 71 loop
--			wait until run='1';
--		end loop;

end;

begin

	process begin
		rst_n <= '0'; wait for CYCLE*3;
		rst_n <= '1'; wait;
	end process;

	process begin
		clk <= '0'; wait for CYCLE/2;
		clk <= '1'; wait for CYCLE/2;
	end process;

-- 3.57MHz
	process(rst_n, clk) begin
		if(rst_n='0') then
			count <= "0000";
		elsif(clk'event and clk='1') then
			if(run='1') then
				count <= "0000";
			else
				count <= count + "0001";
			end if;
		end if;
	end process;
--	run <= '1' when count="1101" else '0'; -- 14-1
	run <= '1' when count="0010" else '0'; -- /4

	VRC7 : vrc7_fifo port map(
		p_reset => rst_n, --: in std_logic;
		m_clock => clk,   --: in std_logic;
		run     => run,   --: in std_logic;
		ready   => '0',   --: in std_logic;
		A       => sel,   --: in std_logic;
		D       => data,  --: in std_logic_vector(7 downto 0);
		write   => we,    --: in std_logic;
		sound   => sound  --: out std_logic_vector(9 downto 0);
	);

-- 1.78MHz
	process(rst_n, clk) begin
		if(rst_n='0') then
			cpu_count <= "00000";
		elsif(clk'event and clk='1') then
			if(cpu_run='1') then
				cpu_count <= "00000";
			else
				cpu_count <= cpu_count + "00001";
			end if;
		end if;
	end process;
--	cpu_run <= '1' when cpu_count="11011" else '0'; -- 28-1
	cpu_run <= '1' when cpu_count="00101" else '0'; -- /4

	process begin
		we <= '0';
		sel <= '0';
		data <= (others=>'Z');
		wait for CYCLE*5;

		write(X"00", X"22", we, sel, data);
		write(X"01", X"61", we, sel, data);
		write(X"02", X"1B", we, sel, data);
		write(X"03", X"05", we, sel, data);
		write(X"04", X"C0", we, sel, data);
		write(X"05", X"A1", we, sel, data);
		write(X"06", X"F8", we, sel, data);
		write(X"07", X"E8", we, sel, data);

		write(X"30", X"03", we, sel, data);
		write(X"20", X"09", we, sel, data);
		write(X"10", X"11", we, sel, data);
		write(X"20", X"19", we, sel, data);

--		wait;-- for 500 us;

--		write(X"31", X"03", we, sel, data);
--		write(X"21", X"09", we, sel, data);
--		write(X"11", X"41", we, sel, data);
--		write(X"21", X"19", we, sel, data);
--		wait for 500 us;

--		write(X"32", X"03", we, sel, data);
--		write(X"22", X"09", we, sel, data);
--		write(X"12", X"A1", we, sel, data);
--		write(X"22", X"19", we, sel, data);

		wait;
	end process;

	process begin
		init_signal_spy("/vrc7/vm2413inf/oc/slot", "slot");
		init_signal_spy("/vrc7/vm2413inf/oc/stage", "stage");
		wait;
	end process;

	sound_en <= '1' when slot=0 and stage=3 else '0';

	process(sound_en)
		variable line_out : line;
		file out_file : text open write_mode is "out_sound.dat";
	begin
		if(sound_en'event and sound_en='1') then
--			write(line_out, to_hstring(sound(11 downto 0)));
			write(line_out, hstr(sound(11 downto 0)));
			writeline(out_file, line_out);
		end if;
	end process;

end SIM;

configuration cfg_vrc7_test of vrc7_tb is
	for SIM end for;
end cfg_vrc7_test;