Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                     563  out of   3072    18%  
 Number of Slice Flip Flops:           453  out of   6144     7%  
 Number of 4 input LUTs:              1014  out of   6144    16%  
 Number of bonded IOBs:                 64  out of    329    19%  
 Number of BRAMs:                        2  out of     16    12%  
 Number of GCLKs:                        1  out of      4    25%  


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
m_clock                            | BUFGP                  | 455   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------

   Minimum period: 21.159ns (Maximum Frequency: 47.261MHz)
   Minimum input arrival time before clock: 21.313ns
   Maximum output required time after clock: 14.413ns
   Maximum combinational path delay: 14.723ns

=========================================================================


Design Summary:

Logic Utilization:
  Number of Slice Flip Flops:       443 out of  6,144    7%
  Number of 4 input LUTs:           991 out of  6,144   16%
Logic Distribution:
    Number of occupied Slices:                         622 out of  3,072   20%
    Number of Slices containing only related logic:    622 out of    622  100%
    Number of Slices containing unrelated logic:         0 out of    622    0%

Total Number 4 input LUTs:        1,018 out of  6,144   16%
      Number used as logic:                       991
      Number used as a route-thru:                 27
   Number of bonded IOBs:            55 out of    325   16%
      IOB Flip Flops:                              10
   Number of Block RAMs:              2 out of     16   12%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  42,956
Additional JTAG gate count for IOBs:  2,688


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 16     12%
   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         0 out of 1       0%

   Number of External IOBs            55 out of 325    16%
      Number of LOCed IOBs             0 out of 55      0%

   Number of SLICEs                  622 out of 3072   20%


**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       m_clock_BUFGP |      GCLKBUF1| No   |  361 |  0.294     |  0.642      |
+---------------------+--------------+------+------+------------+-------------+