Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                     775  out of   3072    25%  
 Number of Slice Flip Flops:           690  out of   6144    11%  
 Number of 4 input LUTs:              1410  out of   6144    22%  
 Number of bonded IOBs:                 74  out of    329    22%  
 Number of BRAMs:                        2  out of     16    12%  
 Number of GCLKs:                        1  out of      4    25%  


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
m_clock                            | BUFGP                  | 692   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------

   Minimum period: 21.082ns (Maximum Frequency: 47.434MHz)
   Minimum input arrival time before clock: 19.439ns
   Maximum output required time after clock: 18.744ns
   Maximum combinational path delay: 19.099ns

=========================================================================


Design Summary:

Logic Utilization:
  Number of Slice Flip Flops:       676 out of  6,144   11%
  Number of 4 input LUTs:         1,397 out of  6,144   22%
Logic Distribution:
    Number of occupied Slices:                         882 out of  3,072   28%
    Number of Slices containing only related logic:    882 out of    882  100%
    Number of Slices containing unrelated logic:         0 out of    882    0%

Total Number 4 input LUTs:        1,413 out of  6,144   22%
      Number used as logic:                     1,397
      Number used as a route-thru:                 16
   Number of bonded IOBs:            73 out of    325   22%
      IOB Flip Flops:                              14
   Number of Block RAMs:              2 out of     16   12%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  46,961
Additional JTAG gate count for IOBs:  3,552


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 16     12%
   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         0 out of 1       0%

   Number of External IOBs            73 out of 325    22%
      Number of LOCed IOBs             0 out of 73      0%

   Number of SLICEs                  882 out of 3072   28%


**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       m_clock_BUFGP |      GCLKBUF1| No   |  465 |  0.269     |  0.642      |
+---------------------+--------------+------+------+------------+-------------+