Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                     729  out of   3072    23%  
 Number of Slice Flip Flops:           705  out of   6144    11%  
 Number of 4 input LUTs:              1325  out of   6144    21%  
 Number of bonded IOBs:                 74  out of    329    22%  
 Number of BRAMs:                        2  out of     16    12%  
 Number of GCLKs:                        1  out of      4    25%  


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
m_clock                            | BUFGP                  | 707   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------

   Minimum period: 18.858ns (Maximum Frequency: 53.028MHz)
   Minimum input arrival time before clock: 20.089ns
   Maximum output required time after clock: 22.357ns
   Maximum combinational path delay: 21.487ns

=========================================================================


Design Summary:

Logic Utilization:
  Number of Slice Flip Flops:       692 out of  6,144   11%
  Number of 4 input LUTs:         1,300 out of  6,144   21%
Logic Distribution:
    Number of occupied Slices:                         866 out of  3,072   28%
    Number of Slices containing only related logic:    866 out of    866  100%
    Number of Slices containing unrelated logic:         0 out of    866    0%

Total Number 4 input LUTs:        1,337 out of  6,144   21%
      Number used as logic:                     1,300
      Number used as a route-thru:                 37
   Number of bonded IOBs:            73 out of    325   22%
      IOB Flip Flops:                              13
   Number of Block RAMs:              2 out of     16   12%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  46,445
Additional JTAG gate count for IOBs:  3,552


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 16     12%
   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         0 out of 1       0%

   Number of External IOBs            73 out of 325    22%
      Number of LOCed IOBs             0 out of 73      0%

   Number of SLICEs                  866 out of 3072   28%


**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       m_clock_BUFGP |      GCLKBUF1| No   |  471 |  0.298     |  0.661      |
+---------------------+--------------+------+------+------------+-------------+