Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                     804  out of   3072    26%  
 Number of Slice Flip Flops:           441  out of   6144     7%  
 Number of 4 input LUTs:              1437  out of   6144    23%  
 Number of bonded IOBs:                 64  out of    329    19%  
 Number of BRAMs:                        2  out of     16    12%  
 Number of GCLKs:                        1  out of      4    25%  


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
m_clock                            | BUFGP                  | 443   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------

   Minimum period: 21.195ns (Maximum Frequency: 47.181MHz)
   Minimum input arrival time before clock: 35.992ns
   Maximum output required time after clock: 15.176ns
   Maximum combinational path delay: 15.168ns

=========================================================================


Design Summary:

Logic Utilization:
  Number of Slice Flip Flops:       440 out of  6,144    7%
  Number of 4 input LUTs:         1,410 out of  6,144   22%
Logic Distribution:
    Number of occupied Slices:                         808 out of  3,072   26%
    Number of Slices containing only related logic:    808 out of    808  100%
    Number of Slices containing unrelated logic:         0 out of    808    0%

Total Number 4 input LUTs:        1,442 out of  6,144   23%
      Number used as logic:                     1,410
      Number used as a route-thru:                 32
   Number of bonded IOBs:            55 out of    325   16%
      IOB Flip Flops:                               1
   Number of Block RAMs:              2 out of     16   12%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  45,386
Additional JTAG gate count for IOBs:  2,688


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 16     12%
   Number of GCLKs                     1 out of 4      25%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         0 out of 1       0%

   Number of External IOBs            55 out of 325    16%
      Number of LOCed IOBs             0 out of 55      0%

   Number of SLICEs                  808 out of 3072   26%


**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       m_clock_BUFGP |      GCLKBUF1| No   |  361 |  0.213     |  0.586      |
+---------------------+--------------+------+------+------------+-------------+