library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

-- RGBカラーパレットROM
-- ブロックRAMをROMとして使用

entity rgb_rom_16 is
port(
	p_reset : in  std_logic;
	m_clock : in  std_logic;
	adrs    : in  std_logic_vector(7 downto 0);
	din     : in  std_logic_vector(15 downto 0);
	dout    : out std_logic_vector(15 downto 0);
	read    : in  std_logic;
	write   : in  std_logic
);
end;

architecture skin of rgb_rom_16 is

component RAMB4_S16
generic(
	INIT_00 : bit_vector;
	INIT_01 : bit_vector;
	INIT_02 : bit_vector;
	INIT_03 : bit_vector
);
port(
	RST  : in  std_logic;
	CLK  : in  std_logic;
	ADDR : in  std_logic_vector(7 downto 0);
	DI   : in  std_logic_vector(15 downto 0);
	DO   : out std_logic_vector(15 downto 0);
	EN   : in  std_logic;
	WE   : in  std_logic
);
end component;

signal enable : std_logic;

begin

	enable <= read or write;

-- 初期値として各行32バイト、全64色×16ビットを設定
-- 各ワードをアドレス値が大きい方から並べる。（ワード内のビット列は通常どおり）

	BM : RAMB4_S16
	generic map(
		INIT_00 => X"000000000000000A000800100010008800C001400140010300840005004400DB",
		INIT_01 => X"000000000000002400210028002001180190018801C201450107004F001F016D",
		INIT_02 => X"0000000000DB003E00BC00B2013001E901E101DB01DD01DF016700A7006F01FF",
		INIT_03 => X"0000000001B6013F017E017D01FD01FD01F501ED01F601F701B701B7017F01FF"
	)
	port map(
		RST  => '0',
		CLK  => m_clock,
		ADDR => adrs,
		DI   => din,
		DO   => dout,
		EN   => enable,
		WE   => write
	);

end skin;