library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_8x512 is
port(
	m_clock : in  std_logic;
	p_reset : in  std_logic;
	adrs    : in  std_logic_vector(8 downto 0);
	din     : in  std_logic_vector(7 downto 0);
	dout    : out std_logic_vector(7 downto 0);
	read    : in  std_logic;
	write   : in  std_logic
);
end;

architecture RTL of ram_8x512 is

type BRAM_TYPE is array (0 to 2**9-1) of std_logic_vector(7 downto 0);
signal BRAM : BRAM_TYPE;
signal adw, adr : integer range 0 to 2**9-1;

begin

	adw <= conv_integer(adrs);

	process(m_clock) begin
		if(m_clock'event and m_clock='1') then
			if(write='1') then
				BRAM(adw) <= din;
			end if;
			adr <= adw;
		end if;
	end process;

	dout <= BRAM(adr);

end;